The present invention relates to a system for transmitting and receiving information between units through a common bus and more particularly to a stack system for transmitting and receiving information between units connected to the common bus.
A system for communicating information between units (units U1 to U6) having processors conducted through a common bus (CBUS), as shown in FIG. 1, has been developed in order to increase data transmission speed and data processing speed. In such a system, units U1 to U6 comprise a CPU, a channel unit, a memory control unit, and so on. When units U1 to U6 obtain the right to use the common bus, the output of data from the common bus is controlled by the internal condition of the unit.
Even if data is communicated from one unit to another in such a common bus system, sometimes the common bus cannot be used instantly when it is being used by the other unit or when its right of use for transmission of data has been obtained by the other unit.
When the common bus can not be used instantly as described above, the unit has to wait for the other unit to finish using the common bus. When a request is made to use the common bus to transmit the result obtained by the process of the unit, the next process proceeds after the transmission from the unit is completed or after the transmission using the common bus is ended. However, when it proceeds to the next process after transmission of the data obtained by the process of the unit is completed, as stated above, then the whole process becomes slow. There has been developed a prior art system in which the processes up to the formation of the next transmission data are conducted in parallel in a plurality of units, and a plurality of transmission data are stored.
In such a system, in order to temporarily maintain the transmission data until the right of use of the common bus can be obtained, a stack is formed by a register or random access memory.
FIG. 2 shows a block diagram of the prior art system. Data register (DTR) 10 is a register for storing data to be transmitted, which are created by processes which will be explained later. Where the common bus 6 is being used by the other unit, the present unit has to wait until the use of the common bus is ended. Therefore, data is stored in data stack (DSTK) 11 during the period of use of common bus 6. Similarly, where the command is added to command register (CMDR) 12 through common bus input circuit 4 and command executing control circuit 5 and then the common bus is being used in by the other unit as is similar to the above case, the content of command register 12 is stored in the command stack (CSTK) 13. It may be noted that the command exists by itself or is paired with data.
If common bus 6 is not being used, the content of data register 10 and the command of command register 12 is added to bus out register (BOR) 23. The selector circuit (SEL) 9 selects a part of the command of command register 12 and bus out control (BUS-OUT-CONTROL) 14 controls the bus output by using the part of the command. For example, the selector circuit 9 selects a plurality of upper bits of the command and the selected bits forming a portion of the command are decoded by decoder (DECODER) 15. Bus sequence control (BUS SEQUENCE CONTROL) 16 produces a control signal based on the decoded result. Based on the control signal, register 17 comprising a CBSY flip-flop and TAG flip-flops produce sequence signals which are temporarily stored in the interface out register (IFOR) 19, thereby controlling control bus 7 through bus buffers 21 and 22. During the period of control by control bus 7, portions of output from data register 10 and command register 12 are added to bus out register (BOR) 23 and the content of bus out register 23 is outputted on a common bus 6 through buffer 24.
On the other hand, where the common bus 6 is used by another unit, the data is stored in data stack 11 and the command is stored in command stack 13. Command read register (CRAR) 26 and command write register (CWAR) 25 are connected to command stack 13, which changes their addresses by one, every time an access of read or write is conducted. The read or write addresses of command stack register 13 are determined according to the value designated by command write register 25 and command read register 26. For example, where the common bus 6 is used by the other unit as described above, the command input to command register 12 is stored in command stack 13 in the address designated by command write register 25. Command stack 13 naturally stores a plurality of commands. When a process of the other unit is completed, the command stored in command stack 13 is read out by the address value of command read register 26 corresponding to command write register 25. Selector 9 selects a portion of the output of command stack 13. A portion of the command stored in command stack 13 is decoded in a similar manner to the state where the common bus 6 is not used and bus sequence control 16 controls the sequence. The output is applied to control bus 7 by interface output register 19 through register 17. Therefore, control bus 7 is controlled. The content of data stack 11 and the command is outputted to common bus 6 through bus out register 23 and buffer 24. Outputs of command write register 25 and command read register 26 are added to comparator (COMP) 8 in addition to the address terminal of command stack 13. Comparator 8 always compares the read and write addresses and if they are not coincident the command is stored in command stack 13. In order to transmit the command stored in command stack 13 until the read address accords with the write address, the selector circuit selects the output of command stack 13. The output of command stack 13 is thereby transmitted to bus output control 14. When they are coincident, the selector 9 is selected so that the output from command register 12 is transmitted directly to common bus 6 through bus out register 23.
Circuits similar to command write register 25 and command read register 26 are also connected to the address of data stack 11, although they are not shown in FIG. 2. They increment in accordance with the read or write operation, thereby enabling the data to be temporarily stored in, and the data to be read out from, data stack 11. A single command does not always correspond to a single item of data. When one command is stored in command stack 13, a plurality of data corresponding to the command is stored in data stack 11. The reading operation is conducted in a similar manner to the storing operation. Every time one command is read out, a plurality of data corresponding to the command is read out and outputted to common bus 6 through bus out register 23 and buffer 24.
When common bus 6 is being used by the other unit in the above system, the data and command produced in the unit are stored in command stack 13 and data stack 11, and when use of the common bus 6 by the other unit is completed, namely, when the common bus 6 becomes empty, a portion of the command is analyzed by bus out control 14 after it is outputted from command stack 13 and then transmitted to the common bus 6. When a plurality of commands are stored in command stack 13 in the above system, respective commands are analyzed by bus out control 14, namely, common bus control output circuit, and such analysis should be applied to each respective command. Although it is not shown in FIG. 2, a priority circuit is provided to limit the use of common bus 6 and control bus 7. Thus, even if the right of use of the common bus is obtained through the priority circuit, analysis of the command as recited above is necessary in the bus out control circuit 14 after the command is outputted from command stack 13. Therefore, the command or data cannot be transmitted immediately to the common bus 6. Even if the common bus 6 becomes vacant, the command and data cannot be outputted to it immediately, but they can be outputted to it only after a predetermined sequence passes in bus out control 14. Therefore, even if use of the common bus 6 is completed, a portion of the command in command stack 13 should be analyzed to output the command and data from the unit which is next to be used, thereby resulting in a waste of time.
As command stack 13 is provided separately from data stack 11, it is necessary that an address of the command stack 13 is previously made to correspond to the addresses for the maximum length of data in the data stack 11 as shown in FIG. 3. Therefore, the capacity of the data stack becomes extremely big, as shown in FIG. 3. For example, supposing the number of data accompanied by one command is a maximum of 4, and the number of loads in command stack 13 is n, the number of words in data stack 11 is 4n, making the data stack extremely large.
According to the system in which data is stored sequentially in data stack 11 and the address of the command in command stack 13 is not previously made to correspond to the addresses of the data in data stack 11, the difference between the write and read addresses of the data is always monitored with regard to both data stack 11 and command stack 13. Namely, it is necessary to consider, by monitoring both data stack 11 and command stack 13, how many data are required after the command is executed, thereby complicating a command start control. Where the command is executed continuously, as in a pipeline method, it is necessary, by monitoring both data stack 11 and command stack 13, to judge the start of the next command based on the difference between the sum of the data accompanied by the command which is being executed and the number of the vacancy in the data stack, thereby further complicating the system. If the above control is not employed, the capability of the apparatus is low.